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| Twist TG16C554 Quad UART with 16-byte FIFO FEATURES IBM PC/AT and PS/2 compatible Quad UART 16-byte transmit-receive FIFO Selectable receive trigger levels Programmable baud rate generator Modem control signals 3.3V or 5V Operation Advanced CMOS for low power consumption 5, 6, 7, 8 Bit characters selection Even, Odd, No parity, or Force parity generations Status report capability Compatible with industry standard 16C550 UART Hardware and Software compatible with 16C454 On-Chip Power-On-Reset function GENERAL DESCRIPTION The TG16C554 is a quad-channel high performance UART offering data rates up to 1.5Mbps. The TG16C554 is a quad functional upgrade of the industry standard 16C450 with an additional 16-byte transmit and receive FIFO. The TG16C554 performs serial-to-parallel conversions on data received from a peripheral device or modem and parallelto-serial conversion on data received from its CPU. The TG16C554DCQ operates in the continuous interrupt enable mode having IRQSEL internally bonded to VCC, whereas the TG16C554CQ operates under MCR bit-3 control having IRQSEL internally bonded to GND. The TG16C554 is ideally suited for PC, embedded systems and Networking applications, such as high speed COM ports or internal modems. The TG16C554 is available in both a 68-pin PLCC package and a 64-pin TQFP package. It is fabricated in an advanced 0.5 CMOS process to achieve low power drain and high-speed performance. APPLICATIONS High speed modems Serial printers Monitoring equipment Add on I/O cards Serial networking Network Hubs and Routers POS Systems ISDN Products PC-104 Cards Embedded Systems ORDERING INFORMATION Part Number TG16C554CJ TG16C554CQ TG16C554DCQ Package 68-Pin PLCC 64-Pin LQFP 64-Pin LQFP Temperature 0C to 70C 0C to 70C 0C to 70C The C temperature product will operate over the Industrial Temperature range (-40C to +85C ). Contact Factory for 100% testing of Industrial Temperature ranges. Twist Semiconductor believes the information in this document to be accurate and reliable. However, it is subject to change without notice. No responsibility is assumed by Twist Semiconductor for its use, nor for infringement of patent or other rights of third parties. - SEE IMPORTANT NOTICE AT THE END OF THIS DOCUMENT Copyright 1999-2002 Twist Semicondutor PO Box 6038 Fremont, CA 94538 [REV. 1.5] 1 TG16C554 Quad UART with 16-byte FIFO Twist IRQSEL GND 68 67 66 65 64 63 62 61 60 59 58 57 56 9 8 7 6 5 4 3 2 1 -CDD -CDA VCC RXD RXA -RID -RIA D7 D6 D5 D4 D3 D2 D1 D0 -DSRA -CTSA -DTRA VCC -RTSA IRQA -CSA TXA -IOW TXB -CSB IRQB -RTSB GND -DTRB -CTSB -DSRB 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 -DSRD -CTSD -DTRD GND -RTSD IRQD -CSD TXD -IOR TXC -CSC IRQC -RTSC VCC -DTRC -CTSC -DSRC TG16C550CJ 55 54 53 52 51 68-Pin Plastic PLCC Package TG16C554CJ XXXXXX YYMM 50 49 48 47 46 45 44 -RIB -RXRDY -TXRDY RXB GND VCC -CDB Xtal2 RXC -RIC NC Ext/Xtal1 RESET -CDC A2 A1 A0 GND VCC RXD RXA 64 -DSRA -CTSA -DTRA VCC -RTSA IRQA -CSA 56 -RID -CDD -CDA -RIA D7 D6 D5 D3 D4 D1 D2 D0 49 48 -DSRD -CTSD -DTRD GND -RTSD IRQD -CSD 1 64-Pin Plastic TQFP Package TXA -IOW TXB -CSB IRQB -RTSB GND -DTRB -CTSB 8 40 TXD -IOR TXC -CSC IRQC -RTSC VCC -DTRC TG16C554DCQ/CQ XXXXXX YYMM 16 17 24 32 33 -CTSC Ext/Xtal1 RESET 2 Copyright 1999-2002 Twist Semicondutor PO Box 6038 Fremont, CA 94538 -CDC -DSRC -DSRB -CDB Xtal2 GND -RIB RCX -RIC VCC RXB A2 A1 A0 [REV. 1.5] Twist TG16C554 Quad UART with 16-byte FIFO TG16C554 Block Diagram FIFO XTAL2 D7-D0 Modem Interface IRQ A-D -TXRDY -RXTDY Bus Interface RE SET A0-A2 -CS A-D -IO W -IO R IRQ SEL Control and Interrupt Logic Trasmitter ExtClk/ XTAL1 Clock & Baud Rate TXA FIFO Receiver RX A -RTSA, -DTRA -CTSA, -DS RA -RIA , -CDA UAR T-B UAR T-C UAR T-D Copyright 1999-2002 Twist Semicondutor PO Box 6038 Fremont, CA 94538 [REV. 1.5] 3 TG16C554 Quad UART with 16-byte FIFO Pin D3 D4 D5 D6 D7 GND RXA -RIA -CDA 68 1 2 3 4 5 6 7 8 9 64 56 57 58 59 60 14 62 63 64 Type I/O I/O I/O I/O I/O PWR I I I Description Data bus bit-3. See D0 Description. Data bus bit-4. See D0 Description. Data bus bit-5. See D0 Description. Data bus bit-6. See D0 Description. Data bus bit-7. Most significant bit of the data bus. See D0. Supply ground. UART-A, Serial data input. Active low, UART-A ring-detect signal. Twist Active low, UART-A Carrier-detect signal. When low this indicates that Modem or data set has detected the data carrier. -CDA has no effect on the transmitter. Active low, UART-A data-set-ready signal. Active low, UART-A clear-to-send signal. When low this indicates that Modem or data set is ready to exchange data. -CTSA has no effect on the transmitter. Active low, UART-A data-terminal-ready signal. It is set to high (in-active) after a hardware reset or during internal loop-back mode. When low, this output indicates to the Modem or data set that the UART-A is ready to establish a communication link. -DTRA has no effect on the transmitter or receiver. Supply voltage. Active low, UART-A request-to-send signal. It is set to high (in-active) after a hardware reset or during internal loop-back mode. When low, this indicates that Modem or data set is ready to establish a communication link. -RTSA has no effect on the transmitter or receiver. UART-A, Active high interrupt output. This signal goes high (active) when an interrupt condition occurs. Interrupt out is gated with IER bit 0-3 and MCR bit-3. Active low, UART-A chip select. UART-A Serial data output. Active low I/O Write input. CPU is allowed to write data into a selected register. The data write operation, depends upon chip selects (CS A-D) and A0-2 address lines. UART-B Serial data output. Active low, UART-B chip select. -DSRA -CTSA 10 11 1 2 I I -DTRA 12 3 O VCC -RTSA 13 14 4 5 PWR O IRQA 15 6 O -CSA TXA -IOW 16 17 18 7 8 9 I O I TXB -CSB 19 20 10 11 O I 4 Copyright 1999-2002 Twist Semicondutor PO Box 6038 Fremont, CA 94538 [REV. 1.5] Twist Pin IRQB 68 21 64 12 Type O Description TG16C554 Quad UART with 16-byte FIFO UART-B, Active high interrupt output. This signal goes high (active) when an interrupt condition occurs. Interrupt out is gated with IER bit 0-3 and MCR bit-3. Active low, UART-B request-to-send signal. It is set to high (in-active) after a hardware reset or during internal loop-back mode. When low, this indicates that Modem or data set is ready to establish a communication link. -RTSB has no effect on the transmitter or receiver. Supply ground. Active low, UART-B data-terminal-ready signal. It is set to high (in-active) after a hardware reset or during internal loop-back mode. When low, this output indicates to the Modem or data set that the UART-B is ready to establish a communication link. -DTRB has no effect on the transmitter or receiver. Active low, UART-B clear-to-send signal. When low this indicates that Modem or data set is ready to exchange data. -CTSB has no effect on the transmitter. Active low, UART-B data-set-ready signal. Active low, UART-B Carrier-detect signal. When low this indicates that Modem or data set has detected the data carrier. -CDB has no effect on the transmitter. Active low, UART-B ring-detect signal. UART-B, Serial data input. Supply voltage. Not used. See A0 Description. See A0 Description. Register select address line. These address lines from the CPU determine which internal register is accessed. Crystal oscillator input or External clock input pin. This signal input is used in conjunction with XTAL2 to form a feedback circuit for the baud rate generator's oscillator. Two external capacitors (10pF) connected from each side of the XTAL1 and XTAL2 to GND is required to form a crystal oscillator circuit. See typical crystal oscillator circuit illustration. Crystal oscillator output or buffered clock output (when external clock is used as clock source). This pin should be left open when external clock is provided to XTAL1. Active high hardware reset. Resets all internal registers to known value. See Power-on-Reset for further description of this function. -RTSB 22 13 O GND -DTRB 23 24 28 15 PWR O -CTSB 25 16 I -DSRB -CDB 26 27 17 18 I I -RIB RXB VCC N.C. A2 A1 A0 28 29 30 31 32 33 34 19 20 21 22 23 24 I I PWR I I I ExtXTAL1 35 25 I XTAL2 36 26 O RESET 37 27 I Copyright 1999-2002 Twist Semicondutor PO Box 6038 Fremont, CA 94538 [REV. 1.5] 5 TG16C554 Quad UART with 16-byte FIFO Pin -RXRDY 68 38 64 Type O Description Twist Active low, UART A-D "Ored" receive data ready. Receive DMA signaling is available with this pin. In FIFO mode, one of two types of DMA signaling can be selected using FCR bit-3. DMA mode [0]: (FCR bit-3=0) supports single transfer DMA (16C450 mode) in which a transfer is made between CPU bus cycle. -RXRDY pin will be low active when there is at least one character in receive holding register or FIFO. -RXRDY pin will be in-active (high) when there are no more characters in the FIFO or holding register. DMA mode [1]: (FCR bit-3=1) supports multi transfer DMA in which multiple transfers are made continuously until the receive FIFO has been emptied. -RXRDY pin will be low active when trigger level or the time-out has been reached. Active low, UART A-D "Ored" transmitter ready. Transmit DMA signaling is available with this pin. In FIFO mode, one of two types of DMA signaling can be selected using FCR bit-3. DMA mode [0]: (FCR bit-3=0) supports single transfer DMA in which a transfer is made between CPU bus cycle. -TXRDY pin will be low (active) when there are no characters in the transmit FIFO, transmit holding register. DMA mode [1]: (FCR bit-3=1) supports multi transfer DMA in which multiple transfers are made continuously until transmit FIFO has been filled. This pin will become in-active (high) when transmit FIFO is completely full. Supply ground. UART-C, Serial data input. Active low, UART-C ring-detect signal. Active low, UART-C Carrier-detect signal. When low this indicates that Modem or data set has detected the data carrier. -CDC has no effect on the transmitter. Active low, UART-C data-set-ready signal. Active low, UART-C clear-to-send signal. When low this indicates that Modem or data set is ready to exchange data. -CTSC has no effect on the transmitter. Active low, UART-C data-terminal-ready signal. It is set to high (in-active) after a hardware reset or during internal loop-back mode. When low, this output indicates to the Modem or data set that the UART-C is ready to establish a communication link. -DTRC has no effect on the transmitter or receiver. Supply voltage. Active low, UART-C request-to-send signal. It is set to high (in-active) after a hardware reset or during internal loop-back mode. When low, this indicates that Modem or data set is ready to establish a communication link. -RTSC has no effect on the transmitter or receiver. UART-C, Active high interrupt output. This signal goes high (active) when an interrupt condition occurs. Interrupt out is gated with IER bit 0-3 and MCR bit-3. Active low, UART-C chip select. -TXRDY 39 - O GND RXC -RIC -CDC 40 41 42 43 45 29 30 31 PWR I I I -DSRC -CTSC 44 45 32 33 I I -DTRC 46 34 O VCC -RTSC 47 48 35 36 PWR O IRQC 49 37 O -CSC 50 38 I 6 Copyright 1999-2002 Twist Semicondutor PO Box 6038 Fremont, CA 94538 [REV. 1.5] Twist Pin TXC -IOR 68 51 52 64 39 40 Type O I Description UART-C Serial data output. TG16C554 Quad UART with 16-byte FIFO Active low I/O Read input. Enables selected register to output data to D0-7 bus. The data output depends upon chip selects (CS A-D) and A0-2 address lines. UART-D Serial data output. Active low, UART-D chip select. UART-D, Active high interrupt output. This signal goes high (active) when an interrupt condition occurs. Interrupt out is gated with IER bit 0-3 and MCR bit-3. Active low, UART-D request-to-send signal. It is set to high (in-active) after a hardware reset or during internal loop-back mode. When low, this indicates that Modem or data set is ready to establish a communication link. -RTSD has no effect on the transmitter or receiver. Supply ground. Active low, UART-D data-terminal-ready signal. It is set high (in-active) after a hardware reset or during internal loop-back mode. When low, this output indicates to the Modem or data set that the UART-D is ready to establish a communication link. -DTRD has no effect on the transmitter or receiver. Active low, UART-D clear-to-send signal. When low this indicates that Modem or data set is ready to exchange data. -CTSD has no effect on the transmitter. Active low, UART-D data-set-ready signal. Active low, UART-D Carrier-detect signal. When low this indicates that Modem or data set has detected the data carrier. -CDD has no effect on the transmitter. Active low, UART-D ring-detect signal. UART-D, Serial data input. Supply voltage. Active high interrupt mode select (internal pull-down). Active interrupt is selected when this pin is connected to VCC (MCR Bit-3 ignored). Three state interrupt mode is selected when it is left open or connected to GND. Three state interrupt is active when MCR Bit-3 is set to "1" for each individual UART. For the DCQ package, this pin is bonded to VCC, and for the CQ package, it is bonded to GND. Data bus. Eight data lines with tri-state outputs provided as a bi-directional path for data. This pin is the least significant bit of the data bus and the first data bit in a transmit or receive serial data stream. Data bus bit-1. See D0 Description. Data bus bit-2. See D0 Description. PO Box 6038 Fremont, CA 94538 [REV. 1.5] 7 TXD -CSD IRQD 53 54 55 41 42 43 O I O -RTSD 56 44 O GND -DTRD 57 58 61 46 PWR O -CTSD 59 47 I -DSRD -CDD -RID RXD VCC IRQSEL 60 61 62 63 64 65 48 49 50 51 52 - I I I I PWR I D0 66 53 I/O D1 D2 67 68 54 55 I/O I/O Copyright 1999-2002 Twist Semicondutor TG16C554 Quad UART with 16-byte FIFO Twist Internal Registers A2 0 0 0 0 1 1 1 1 0 0 A1 0 0 1 1 0 0 1 1 0 0 A0 0 1 0 1 0 1 0 1 0 1 READ MODE Receive Holding Register Interrupt Enable Register Interrupt Identification Register WRITE MODE Transmit Holding Register Interrupt Enable Register FIFO Control Register Line Control Register Modem Control Register Line Status Register Modem Status Register Scratchpad Register LSB of Divisor Latch MSB of Divisor Latch Scratchpad Register LSB of Divisor Latch MSB of Divisor Latch Divisor Latch registers are only accessible when Line Control Register (LCR) bit-7 is set to a logic 1. 8 Copyright 1999-2002 Twist Semicondutor PO Box 6038 Fremont, CA 94538 [REV. 1.5] Twist Internal Registers Table TG16C554 Quad UART with 16-byte FIFO A2 A1 A0 Register 0 0 0 0 0 0 0 0 1 RHR THR IER BIT-7 bit-7 bit-7 0 BIT-6 bit-6 bit-6 0 BIT-5 bit-5 bit-5 0 BIT-4 bit-4 bit-4 0 BIT-3 bit-3 bit-3 BIT-2 bit-2 bit-2 BIT-1 bit-1 bit-1 BIT-0 bit-0 bit-0 modem receive transmit receive status line holding holding interrupt status register register interrupt DMA mode select INT priority bit-2 parity enable XMIT FIFO reset INT priority bit-1 stop bits RCVR FIFO reset INT priority bit-0 word length bit-1 RTS FIFO enable 0 1 0 FCR RCVR trigger (MSB) RCVR trigger (LSB) 0 0 0 1 0 IIR FIFO FIFO enabled enabled 0 0 INT status 0 1 1 LCR divisor latch enable 0 set break set parity even parity word length bit-0 DTR 1 0 0 MCR 0 0 loop back IRQ enable (OP2) framing error (OP1) 1 0 1 LSR FIFO error transmit transmit break empty holding interrupt empty RI DSR CTS parity error overrun receive error data ready delta -DSR bit-1 bit-1 bit-9 delta -CTS bit-0 bit-0 bit-8 1 1 0 MSR CD delta -CD bit-3 bit-3 bit-11 delta -RI bit-2 bit-2 bit-10 1 0 0 1 0 0 1 0 1 SPR DLL DLM bit-7 bit-7 bit-15 bit-6 bit-6 bit-14 bit-5 bit-5 bit-13 bit-4 bit-4 bit-12 DLL and DLM are accessible only when LCR Bit-7=1. Copyright 1999-2002 Twist Semicondutor PO Box 6038 Fremont, CA 94538 [REV. 1.5] 9 TG16C554 Quad UART with 16-byte FIFO UART OPERATION Transmitter Holding Register (THR) The UART transmitter section of the TG16C554 consists of a transmitter holding register (THR) and a transmitter shift register (TSR). The THR is actually a 16-byte FIFO. Transmitter section control is a function of the UART line control register. The UART THR receives data off the internal data bus and when the shift register is idle, moves it into the TSR. The TSR serializes the data and outputs it at TX. In the 16C450 mode, if the THR is empty and the transmitter holding register empty (THRE) interrupt is enabled (IER-1=1), an interrupt is generated. This interrupt is cleared when a character is loaded into the register. In the FIFO mode, the interrupts are generated based on the control setup in the FIFO control register. Receive Holding Register (RHR) The UART receiver section of the TG16C554 consists of a receiver shift register (RSR) and a receiver Holding register (RHR). The RHR is actually a 16-byte FIFO. Timing to receive holding register is supplied by the 16x-receiver clock. Receiver section control is a function of the UART line control register. The UART RHR receives serial data from RX. The RSR then concatenates the data and moves it into the RHR FIFO. In the 16C450 mode, when a character is placed in the receiver holding register and the received data available interrupt is enabled (IER-0=1), an interrupt is generated. This interrupt is cleared when the data is read out of the receiver holding register. In the FIFO mode, the interrupts are generated based on the control setup in the FIFO control register. Interrupt Enable Register (IER) The interrupt enables register enables each of the five types of interrupts and IRQ pin response to an interrupt generation. The interrupt enable register can also be used to disable the interrupt system by setting bits 0-3 to logic 0. The contents of this register are described below. IER Bit-0: 0 = Disable the received data available interrupt. 1 = Enables the received data available interrupt. IER Bit-1: 0 = Disable the transmitter holding register empty interrupt. 1 = Enable the transmitter holding register empty interrupt. IER Bit-2: 0 = Disables the receiver line status interrupt. 1 = Enables the receiver line status interrupt. IER Bit-3: 0 = Disables the modem status interrupt. 1 = Enables the modem status interrupt. IER Bits 4-7: These bits are not used (always set to 0). Twist Interrupt Identification Register (IIR) The UART has an on chip interrupt generation and prioritization capability that permits a flexible interface with most popular microprocessors. IIR Bit-0: 0 = An interrupt is pending. Used either in a hardware prioritized or polled interrupt system. 1 = No interrupt is pending. IIR Bits 1-2: The UART provides four prioritized levels of interrupts: Priority 1 - Receiver line status (highest priority) (LSR) Priority 2 - Receiver data ready (RXRDY) Priority 2 - Receiver character time-out (RXRDY) Priority 3 - Transmitter holding register empty (TXRDY) Priority 4 - Modem status (lowest priority) (MSR) When an interrupt is generated, the interrupt identification register indicates that an interrupt is pending and encodes the type of interrupt in its three least significant bits (bits 0, 1, and 2). Interrupt Priority decode Bit-3 Bit-2 0 0 1 0 0 1 1 1 0 0 Bit-1 1 0 0 1 0 Bit-0 0 0 0 0 0 Interrupt source Receive line status register Receive data ready Receive time-out Transmit holding empty Modem status register The bits are used to identify the highest priority interrupt pending. 10 Copyright 1999-2002 Twist Semicondutor PO Box 6038 Fremont, CA 94538 [REV. 1.5] Twist IIR Bit-3: 0 = In the 16C450 mode. In FIFO mode, this bit is set along with bit-2 to indicate that a time-out interrupt is pending. IIR Bits 4-5: These bits are not used (always reset at 0). IIR Bits 6-7: 0 = In the 16C450 mode. 1 = When FCR-0 is equal to 1. FIFO control register (FCR) The FIFO control register (FCR) is a write only register. The (FCR) enables and clears the FIFO; sets receive FIFO trigger level, and selects the type of DMA signaling. FCR Bit-0: 0 = 16C450 mode, disables the transmitter and receiver FIFO. 1 = Enables the transmitter and receiver FIFO. This bit must be set to 1 when other (FCR) bits are written to or they are not programmed. Changing this bit clears the FIFO. FCR Bit-1: 0 = Normal operation 1 = Clears all bytes in the receiver FIFO and resets its counter logic to 0. The shift register is not cleared. The one that is written to this bit position is self-clearing. FCR Bit-2: 0 = Normal operation 1 = Clears all bytes in the transmit FIFO and resets its counter logic to 0. The shift register is not cleared. The one that is written to this bit position is self-clearing. FCR Bit-3: 0 = Mode [0]: Supports single transfer DMA (16C450 mode) in which a transfer is made between CPU bus cycle. -RXRDY Pin: Will be active low when there is at least one character in the receive holding register or FIFO. -RXRDY pin will be inactive (high) when there are no more characters in the FIFO or holding register. This pin will also be active low when trigger level or the time-out has been reached. Supports multi-transfer DMA in which multiple transfers are made continuously until transmit FIFO has been filled. This pin will become inactive (high) when transmit FIFO is completely full or reached trigger level. Copyright 1999-2002 TG16C554 Quad UART with 16-byte FIFO -TXRDY Pin: This pin will be active low until transmit FIFO has been filled. This pin will become inactive (high) when transmit FIFO is completely full. It will also be active low when no characters are in the transmit FIFO, transmit holding register. 1 = Mode [1]: Supports multi transfer DMA in which multiple transfers are made continuously until the receive FIFO has been emptied. FCR its 4-5: These bits are not used. FCR Bits 6-7: These bits are used to set the trigger level for the receiver FIFO interrupt. Receive trigger levels (BYTES) Bit-7 0 0 1 1 Bit-6 0 1 0 1 RX FIFO trigger level 1 4 8 14 Line Control Register (LCR) The system programmer controls the format of the asynchronous data communication exchange through the line control register. In addition, the programmer is able to retrieve, inspect, and modify the contents of the line control register; this eliminates the need for separate storage of the line characteristics in system memory. LCR Bits 0-1: These two bits specify the number of bits in each transmitted or received serial character. Word Length Bit-1 0 0 1 1 Bit-0 0 1 0 1 Word length 5 6 7 8 bits bits bits bits Twist Semicondutor PO Box 6038 Fremont, CA 94538 [REV. 1.5] 11 TG16C554 Quad UART with 16-byte FIFO LCR Bit-2: This bit specifies, 1, 1-1/2, or 2 stop bits in each transmitted character. When bit-2 is reset to 0, one stop bit is generated in the data. When bit-2 is set to 1, the number of stop bits generated is dependent on the word length selected with bits 0 and 1. The receiver clocks only the first stop bit regardless of the number of stop bits selected. The number of stop bits generated in relation to word length and bit-2. Stop Bits Bit-2 0 1 1 1 1 Word length X 5 bits 6 bits 7 bits 8 bits Stop bit(s) 1 1-1/2 2 2 2 Twist LCR Bit-6: 0 = Normal operation. Break condition is disabled and has no effect on the transmitter logic. 1 = Force a break condition. A condition where TX is forced to the space (low) state. LCR Bit-7: 0 = Normal operation. 1 = Divisor latch enable. Must be set to 1 to access the divisor latches of the baud generator during a read or write. Bit-7 must be reset to 0 during a read or write to the receiver holding, the transmitter holding register, or the interrupt enable register. Modem Control Register (MCR) The modem control register is an 8-bit register that controls an interface with a modem, data set, or peripheral device that is emulating a modem. MCR Bit-0: 0 = Sets the -DTR output pin to high. 1 = Sets the -DTR output pin to low. MCR Bit-1: 0 = Sets the -RTS output pin to high. 1 = Sets the -RTS output pin to low. MCR Bit-2: 0 = Sets the -OP1 to high during loop-back mode. 1 = Sets the -OP1 to low during loop-back mode. MCR Bit-3: 0 = Sets IRQ output pin to three sate. Sets the -OP2 to high during loop-back mode. 1 = Sets IRQ output pin to active mode. Sets the -OP2 to low during loop-back mode. MCR Bit-4: 0 = Normal operation. 1 = Internal loop back mode. Provides a local loop-back feature for diagnostic testing of the UART. When LOOP is set to 1, the following occurs: The transmitter TX pin is set to high. The receiver RX pin is disconnected. The output of the transmitter shift register is looped back into the receiver shift register input. The four modem inputs (-CTS, -DSR -CD and -RI) pins are disconnected. The four modem outputs (-DTR, -RTS, OP1, and -OP2) pins are internally connected to the four modem inputs. The four modem outputs are forced to high levels. PO Box 6038 Fremont, CA 94538 [REV. 1.5] LCR Bit-3: 0 = Parity is disabled. No parity is generated or checked. 1 = Parity bit is generated in transmitted data between the last data word bit and the first stop bit. In received data, parity is checked. LCR Bit-4: 0 = ODD parity select bit. When parity is enabled by bit-3, a 1 in bit-4 produces odd parity (an odd number of 1's in the data and parity bits. 1 = Even parity select bit. When parity is enabled by bit-3, a 1 in bit-4 produces even parity (an even number of 1's in the data and parity bits). LCR Bit-5: 0 = Stick parity is disabled. 1 = Stick parity bit. When bits 3-5 are set to 1 the parity bit is transmitted and checked as a 0. When bits-3 and 5 are 1's and bit-4 is a 0, the parity bit is transmitted and checked as 1. Parity selection Bit-5 X 0 0 1 1 Bit-4 X 0 1 0 1 Bit-3 0 1 1 1 1 Parity type No parity Odd parity Even parity Forced parity "1" Forced parity "0" 12 Copyright 1999-2002 Twist Semicondutor Twist In the diagnostic mode, data that is transmitted is immediately received. This allows the processor to verify transmit and receive data paths to the UART. The receiver and transmitter interrupts are fully operational. The modem control interrupts are also operational, but the modem control interrupt sources are now the lower four bits of the modem control register instead of the four modem control inputs. All interrupts are still controlled by the interrupt enable register. MCR bits 5-7: These bits are not used. Line Status Register (LSR) The line status register provides information to the CPU concerning the status of data transfers. The line status register is intended for read operations only; writing to this register is not recommended. Bits 1-4 are the error conditions that produce a receiver line status interrupt. LSR Bit-0: 0 = No data in receive holding or FIFO. 1 = Data ready indicator for the receiver. This bit is set to 1 whenever a complete incoming character has been received and transferred into the receiver holding register or the FIFO. It is reset to 0 by reading all of the data in the receiver holding register or the FIFO. LSR Bit-1: 0 = Normal operation. No overrun error. 1 = It indicates that before the character in the receiver holding register was read, it was over written by the next character transferred into the register. OE is reset every time the CPU reads the contents of the line status register. If the FIFO mode data continues to fill the FIFO beyond the trigger level, an overrun error occurs only after the FIFO is full and the next character has been completely received in the shift register. An overrun error is indicated to the CPU as soon as it happens. The character in the shift register is overwritten, but it is not transferred to the FIFO. LSR Bit-2: 0 = Normal operation. No parity error. 1 = It indicates that the parity of the received data character does not match the parity selected in the line control register. PE is reset every time the CPU reads the contents of the line status register. In the FIFO mode, this error is associated with the particular character in the FIFO to which it applies. This error is revealed to the CPU when its associated character is at the top of the FIFO. Copyright 1999-2002 TG16C554 Quad UART with 16-byte FIFO LSR Bit-3: 0 = Normal operation. No framing error. 1 = It indicates that the received character did not have a valid stop bit. FE is reset every time the CPU reads the contents of the line status register. In the FIFO mode, this error is associated with the particular character in the FIFO to which it applies. This error is revealed to the CPU when its associated character is at the top of the FIFO. The UART tries to re-synchronize after a framing error. To accomplish this, it is assumed that the framing error is due to the next start bit. LSR Bit-4: 0 = Normal operation. 1 = It indicates that the received data input was held in the logic low state for longer than a full word transmission time. A full word transmission time is defined as the total time to transmit the start, data, parity, and stop bits. BI is reset every time the CPU reads the contents of the line status register. In the FIFO mode, this error is associated with the particular character in the FIFO to which it applies. This error is revealed to the CPU when its associated character is at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. LSR Bit-5: 0 = At least one byte is written to the transmit FIFO or transmit holding register. 1 = Transmitter holding register is empty, indicating that the UART is ready to accept a new character. If the THRE interrupt is enabled when THRE is set to 1, an interrupt is generated. THRE is set to 1 when the contents of the transmitter holding register are transferred to the transmitter shift register. LSR Bit-6: 0 = When either the transmitter holding register or the transmitter shift register contains a data character. 1 = Transmitter holding register and the transmitter shift register are both empty. LSR Bit-7: 0 = In the 16C450, this bit is always reset to 0. 1 = In the FIFO mode, at least one parity, framing, or break error in the FIFO. It is cleared when the microprocessor reads the LSR and there are no subsequent errors in the FIFO. Twist Semicondutor PO Box 6038 Fremont, CA 94538 [REV. 1.5] 13 TG16C554 Quad UART with 16-byte FIFO Modem Status Register (MSR) The modem status register is an 8-bit register that provides information about the current state of the control lines from the modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provide change information, when input from the modem changes state, the appropriate bit is set to 1. All four bits are reset to 0 when the CPU reads the modem status register. MSR Bit-0: 0 = No change to -CTS input. 1 = Indicates that the -CTS input has changed state since the last time it was read by the CPU. When interrupt is enabled, a modem status interrupt is generated. MSR Bit-1: 0 = No change to -DSR input. 1 = Indicates that the -DSR input has changed state since the last time it was read by the CPU. When interrupt is enabled, a modem status interrupt is generated. MSR Bit-2: 0 = No change to -RI input. 1 = Indicates that the -RI input has changed from a low to a high level. When -RI is set to 1 and the modem status interrupt is enabled, a modem status interrupt is generated. MSR Bit-3: 0 = No change to -CD input. 1 = Indicates that the -CD input has changed state since the last time it was read by the CPU. When interrupt is enabled, a modem status interrupt is generated. MSR Bit-4: Complement of the clear to send (-CTS) input. When the UART is in the diagnostic test mode, it is equal to -RTS. MSR Bit-5: Complement of the data set ready (-DSR) input. When the UART is in the diagnostic test mode, it is equal to -DTR. MSR Bit-6: Complement of the ring indicator (-RI) input. When the UART is in the diagnostic test mode, it is equal to -OP1. MSR Bit-7: Complement of data carrier detect (-CD) input. When the UART is in diagnostic test mode, it is equal to -OP2. Twist Scratch Pad Register (SPR) The scratch pad register is an 8-bit register that is intended for programmer use as a scratch pad in the sense that it temporarily holds the programmer data without affecting any other UART operation. Programmable Baud-Rate Generator The UART contains a programmable baud generator that takes a clock input in the range between 1 MHz and 24 MHz and divides it by a divisor in the range between 1 and (216-1). The output frequency of the baud generator is 16 times the baud rate. Two 8-bit registers, called divisor latches, store the divisor in a 16-bit binary format. These divisor latches must be loaded during initialization of the UART in order to ensure desired operation of the baud generator. When either of the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load. Baud rate generator programming table @ 1.8432 MHz Baud Out 115.2k 57.6k 38.4k 19.2 9600 2400 1200 600 300 150 50 DLM (hex) 00 00 00 00 00 00 00 00 01 03 09 DLL (hex) 01 02 03 06 0C 30 60 C0 80 00 00 FIFO interrupt mode operation When the receiver FIFO and receiver interrupts are enabled (FCR-0=1, IER-0=1, IER-2=1), a receiver interrupt occurs as follows: The received data available interrupt issued to the microprocessor when the FIFO has reached its programmed trigger level. It is cleared when the FIFO drops below its programmed trigger level. The IIR receive data available indication also occurs when the FIFO trigger level is reached, and like the interrupt, it is cleared when the FIFO drops below the trigger level. 14 Copyright 1999-2002 Twist Semicondutor PO Box 6038 Fremont, CA 94538 [REV. 1.5] Twist The receiver line status interrupt has higher priority than the received data available interrupt. The data ready bit (LSR-0) is set when a character is transferred from the shift register to the receiver FIFO. It is reset when the FIFO is empty. When the receiver FIFO and receiver interrupts are enabled, FIFO time-out interrupt occurs when the following conditions exist: At least one character is in the FIFO. The most recent serial character was received more than four continuous character times ago (if two stop bits are programmed, the second one is included in this time delay). The most recent microprocessor read of the FIFO occurred more than five continuous character times ago. When a time-out interrupt has occurred, it is cleared and the timer is reset when the microprocessor reads one character from the receiver FIFO. When a time-out interrupt has not occurred, the time-out timer is reset after a new character is received or after the microprocessor reads the receiver FIFO. When the transmitter FIFO and THRE interrupt are enabled (FCR-0=1, IER-1=1), transmit interrupts occur as follows: The occurrence of transmitter holding register empty interrupt is delayed one character time minus the last stop bit time when there have not been at least two bytes in the transmitter FIFO at the same time since the last time the transmitter FIFO was empty. It is cleared as soon as the transmitter holding register is written to (1 to 16 characters may be written to transmit FIFO while servicing this interrupt) or the IIR is read. The first transmitter interrupt after changing FCR is immediate if it is enabled. The transmitter empty indicator is delayed one character time when there has not been at least two bytes in the transmitter FIFO at the same time since the last time that TEMT=1. TEMT is set after the stop bit has been completely shifted out. The transmitter FIFO empty indicator works the normal way in this mode and is not delayed. Character time-out and receiver FIFO trigger-level interrupts have the same priority as the current received data available interrupt. C1 10 - 22 pf TG16C554 Quad UART with 16-byte FIFO Power-On-Reset. The TG16C554 has a built in POR function. This function allows the RESET pin to be permanently tied low. Upon power-on, a 2 s reset pulse is internally generated to reset the device. If this pin is not tied low, a 2 s reset pulse is created if the incoming reset is less than 2 s in duration. Master rest conditions Register IER FCR IIR IIR LCR MCR LSR LSR LSR MSR SPR DLL DLL DLM Bits Bit 7-0 Bit 7-0 Bit 0 Bit 7-1 Bit 7-0 Bit 7-0 Bit 4-0 Bit 6-5 Bit 7 Bit 3-0 Bit 7-0 Bit 0 Bit 7-1 Bit 7-0 State 0 0 1 0 0 0 0 1 0 0 AA 1 0 0 XTAL1 XTAL2 R2 R1 1M 50 - 150 1.8432 MHz C2 10 - 22 pf Typical Crystal Oscillator Circuitry Copyright 1999-2002 Twist Semicondutor PO Box 6038 Fremont, CA 94538 [REV. 1.5] 15 TG16C554 Quad UART with 16-byte FIFO Twist Absolute Maximum Ratings Supply Range Voltage at any pin Operating Temperature Storage Temperature Package Dissipation ESD Latch up 6 Volts GND - 0.3 to VCC +0.3 -40 C to 85 C -65 C to 150 C 750 mW 2000 Volts 220 mA DC Electrical Specifications T=0C to 70C (T=-40C to +85C for industrial tested "I" grade parts), VCC=3.3V to 5V10% unless otherwise specified. Symbol Parameter Limits 3.3V Min Max -0.3 2.0 -0.3 2.0 0.6 VCC 0.8 VCC Limits 5V Min Max -0.5 2.4 -0.5 2.4 0.6 VCC 0.8 VCC 0.4 Unit Condition Viclk Vihck Vil Vih Vol Vol Voh Voh Iil Icc Cp Clock input low level Clock input high level Input low level Input high level Output low level Output low level Output high level Output high level Input leakage current Operating current Input pin Capacitance V V V V V V V V External clock External clock 0.4 2.4 2.0 10 3 5 10 5 5 Iol = 6 mA Iol = 4 mA Ioh = -6 mA Ioh = -4 mA A mA pF 16 Copyright 1999-2002 Twist Semicondutor PO Box 6038 Fremont, CA 94538 [REV. 1.5] Twist TG16C554 Quad UART with 16-byte FIFO AC Electrical Specifications T= 0C to 70C (T=-40C to +85C for industrial tested "I" grade parts), VCC=3.3V to 5V10% unless otherwise specified. Limits 3.3V Min Max 2500 60 8 0 8 40 15 25 10 8 15 40 20 15 40 8 8 9 40 1 8 9 50 40 40 20 20 16 17 17 28 8 8 5 10 35 15 10 35 8 9 35 1 9 45 35 35 Limits 5V Min Max 2000 50 5 0 5 35 10 20 5 Symbol Parameter Unit Condition T1w T5w T5s T6h T7s T9w T10h T12s T13h T15s T17h T19w T20s T21h T22d T23d T24d T25d T26d T27d T28d T29d T30d T31w T32w T33 Reset strobe width -CS A-D strobe width Chip select setup time Chip select hold time -IOR setup time -IOR strobe width -IOR hold time D0-D7 setup time D0-D7 hold time -IOW setup time -IOW hold time -IOW strobe width D0-D7 setup time D0-D7 hold time Delay from THR write to -TXRDY high Delay from Start bit to -TXRDY low Delay from Stop bit to set interrupt Delay from RHR read to Reset interrupt Delay from Stop bit to set -RXRDY low Delay from RHR trigger Level to -RXRDY low Modem output delay Delay from Modem input Change to interrupt Delay from MCR read to Clear interrupt Clock pulse duration Clock pulse duration Clock frequency ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Rclk Rclk ns Rclk Rclk ns ns ns ns ns MHz -AS=0 -AS=0 -AS=0 -AS=0 100 pf load 100 pf load 100 pf load 100 pf load Copyright 1999-2002 Twist Semicondutor PO Box 6038 Fremont, CA 94538 [REV. 1.5] 17 TG16C554 Quad UART with 16-byte FIFO Twist A2-A0 Valid T11h -CS A-D T7s T8s Valid T10h T9w -IOR T12s T13h Valid Data D7-D0 -IOW 554-00 Figure 1. Read Cycle Timing Waveform A2-A0 Valid T18h -CS A-D T15s T16s Valid T17h T19w -IOW T20s T21h Valid Data D7-D0 -IOR 554-01 Figure 2. Write Cycle Timing Waveform 18 Copyright 1999-2002 Twist Semicondutor PO Box 6038 Fremont, CA 94538 [REV. 1.5] Twist TG16C554 Quad UART with 16-byte FIFO -IOW TX A-D Data T22d Parity Stop Start T23d -TXRDY 554-03 Figure 3. Transmitter Ready Mode "0" Timing Waveform -IOW Data #16 TX A-D Data T22d Parity Stop Start T23d -TXRDY FIFO Full 554-04 Figure 4. Transmitter Ready Mode "1" Timing Waveform Copyright 1999-2002 Twist Semicondutor PO Box 6038 Fremont, CA 94538 [REV. 1.5] 19 TG16C554 Quad UART with 16-byte FIFO Twist RX A-D Start #1 Data 5-8 Parity T24d Stop Start #2 IRQ A-D T25d -IOR RHR Registers 554-05 Figure 5. Receive Ready Mode "0" Timing Waveform Trigger Level RX A-D Start n Data 5-8 Parity Stop T27d Start n+1 Data 5-8 IRQ A-D T25d RHR Empty -IOR 554-06 Figure 6. Receive Ready Mode "1" Timing Waveform 20 Copyright 1999-2002 Twist Semicondutor PO Box 6038 Fremont, CA 94538 [REV. 1.5] Twist TG16C554 Quad UART with 16-byte FIFO -IOW T28d T28d -RTS A-D -DTR A-D -CTS A-D -DSR A-D -CD A-D -RI A-D T29d T29d IRQ A-D T30d -IOR 554-07 Figure 7. Modem Control Timing Waveform T31w T32w ExtClk/ XTAL1 T33 554-10 Figure 8. Clock Timing Waveform Copyright 1999-2002 Twist Semicondutor PO Box 6038 Fremont, CA 94538 [REV. 1.5] 21 TG16C554 Quad UART with 16-byte FIFO 68-Pin Plastic PLCC Package Outline Twist D D1 45 9 10 1 61 60 E1 E 26 27 43 44 A1 A e 0.33/0.53 0.013/0.021 D2 0.66/0.81 0.026/0.032 0.51/0.71 0.020/0.028 MILLIMETER SYMBOL A A1 e D/E D1/E1 D2 25.02 24.13 22.40 MIN 4.19 2.29 1.27 TYP 25.40 24.33 23.82 MAX 5.08 3.30 MIN 0.165 0.090 INCH MAX 0.200 0.130 0.050 TYP 0.985 0.950 0.882 1.000 0.958 0.948 22 Copyright 1999-2002 Twist Semicondutor PO Box 6038 Fremont, CA 94538 [REV. 1.5] Twist TG16C554 Quad UART with 16-byte FIFO 64-Pin Plastic TQFP Package Outline 10x10x1.4 mm HE E 64 1 49 48 D HD 16 17 32 33 e b A2 A1 c L MILLIMETER SYMBOL A1 A2 b c e L HD/HE D/E 0.45 11.80 9.90 MIN 0.05 1.35 0.17 0.09 MAX 0.15 1.45 0.27 0.20 0.50 TYP 0.75 12.20 10.10 0.018 0.465 0.390 MIN 0.002 0.053 0.007 0.004 INCH MAX 0.006 0.057 0.011 0.008 0.020 TYP 0.030 0.480 0.398 Copyright 1999-2002 Twist Semicondutor PO Box 6038 Fremont, CA 94538 [REV. 1.5] 23 Twist Semiconductor IMPORTANT NOTICES Twist Semiconductor is a division of Twist Group, Incorporated. Twist's products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of Twist Group, Incorporated. Life support devices or systems are applications that may involve potential risks of death, personal injury, or severe property or environmental damages. These critical components are semiconductor products whose failure to perform can be reasonably expected to cause the failure of the life support system or device or to adversely impact its effectiveness or safety. The use of Twist Semiconductor's products in such devices or systems is done so fully at the customer's risk and liability. As in all designs and applications, it is recommended that the customer apply sufficient safeguards and guardbands in both the design and operating parameters. Twist Semiconductor assumes no liability for customer applications assistance nor for customer's product design(s) that use Twist's products. Twist Semiconductor warrants the performance of its products to the current specifications in effect at the time of sale per Twist's standard limited warranty. Twist Semiconductor imposes testing and quality control processes that it deems necessary to support this warranty. The customer should be aware that not all parameters are 100% tested for each device. Sufficient testing is done to insure product reliability in accordance with Twist's warranty. Twist Semiconductor believes the information in this document to be accurate and reliable, but assumes no responsibility for any errors or omissions that may have occurred in its generation or printing. However, it is subject to change without notice. No responsibility is assumed by Twist Semiconductor to update or keep current the information contained in this document, or for its use, or for infringement of patent or other rights of third parties. Twist Semiconductor does not warrant or represent that any license, either expressed or implied, is granted to the user. IBM PC/AT and PS/2 are Trademarks of International Business Machines Corporation. CENTRONICS is the Trademark of Centronics Data Computer Corporation. Copyright 1999-2002 Twist Semiconductor PO Box 6038 Fremont, CA 94538 [REV. 1.5] 24 |
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